1. Field of the Invention
The present invention relates to a flash memory device, and more particularly to a flash memory device which has a switching circuit for applying a voltage to wells with a time interval when flash memory cells which have a triple well structure are erased.
2. Description of the Prior Art
In general, a memory device such as flash electrically erasable and programmable read only memory (EEPROM) has both functions of electrically programming and erasing, and is classified into a the stack-gate type and the split-gate type depending on a shape of gate electrode thereof. Now, details of the conventional stack-gate flash memory cell will be described with reference to FIG. 1.
In the conventional stack-gate type flash memory cell, as shown in FIG. 1, a tunnel oxide layer 3, a floating gate 4, a dielectric layer 5 and a control gate 6 are sequentially stacked on a silicon substrate 1 in which a well 2 is formed to form a gate electrode. Impurity ions are injected into the substrate 1 at both sides of the gate electrode, therefore a source 7 and a drain 8 are formed. The operation of programming and erasing of the flash memory cell as described above will be described with reference to FIG. 2 to FIG. 4.
To program an information to the flash memory cell, that is, to charge electric charge to the floating gate 4, a higher voltage V.sub.G of 9V is applied to the control gate 6, a supply voltage V.sub.D of 5V is applied to the drain 8, and the source 7 and the well 2 are grounded, respectively, as shown in FIG. 2. Then, channel is formed between the source 7 and the drain 8 due to the higher voltage V.sub.G applied to the control gate 6, and high electric field zone is formed on the substrate 1 at the side of the drain 6 due to the supply voltage V.sub.D applied to the drain 8. At this time, a part of electrons existing in the channel receive an energy from the high electric field zone and become hot electrons, and a part of the hot electrons are injected into the floating gate 4 through the tunnel oxide layer 3 by an electrical field formed in a vertical direction due to the high voltage applied to the control gate 6. Accordingly, a threshold voltage V.sub.T of the flash memory cell rises by such injection of hot electrons.
To erase the information programmed in the flash memory cell, that is, to discharge electric charge stored in the floating gate 4, a negative voltage V.sub.G of -8V is applied to the control gate 6, voltage V.sub.S of 5V is applied to the source 7, and the drain 8 and the well 2 are grounded, respectively, as shown in FIG. 3 and FIG. 4. Then, the electrons injected into the floating gate 3 are moved to the source 7 due to the F-N (fowler-nordheim) tunneling phenomenon, so that threshold voltage V.sub.T of memory cells is lowered.
When the erasing operation is performed, a band to band leakage current occurs by the electric field formed between the floating gate 4 and the source 7, and the band to band leakage current is accelerated by the voltage between the source 7 and the well 2, whereby the current is increased. Also, the generated holes pass through the tunnel oxide layer 3 and are injected into the floating gate 4, or trapped in the tunnel oxide layer 3 adjacent to the source 7. By such phenomenon, an over erasing occurs or characteristic of cycling is degraded.
To prevent such phenomenon, the source 7 is formed with the double diffused drain (DDD) structure. However, a high integration of device is difficult due to a side diffusion of impurity ions.